1 Synchronization Mode Four different modes may be defined under user control. The TRIG1 and TRIG2 signals may be used to trigger external events and to control the integration time. The Master clock is either external or internal clock

2 Free Run Mode with Integration Time Setting The integration and readout periods start automatically and immediately after the previous period. The read-out time depends on pixel number and pixel rate.

3 Trigger and Integration Time Controlled by One Input The integration period starts immediately after the falling edge of TRIG1 input signal, stops immediately after the rising edge of TRIG1 input signal, and is immediately followed by a readout period. The readout time depends on pixel number and pixel rate

4 Trigger and Integration Time Controlled by Two Inputs TRIG2 rising edge start the integration period. TRIG1 rising edge stop the integration period. This period is immediately followed by a readout period.

5. Timing Diagram Note: CLK_IN input frequency must be in the range 5 to 60 MHz. Out of this range, the performances may be decreased. In case of multi-cameras synchronization (means more than one camera on one acquisition board): ? the "master" camera will provide DATA, STROBE and LVAL signals to the acquisition board. The others will only provide DATA. ? the external clock CLK_IN must be input on each cameras to guaranty perfect data synchronization. ? the trigger(s) input (TRIG1 and/or TRIG2) must be input on each cameras. It is recommended to synchronize the rising edge of these signals on the CLK_IN falling edge. ? cables must be balanced between each cameras (same quality, same length) to ensure perfect cameras synchronization. ? the CLK_IN frequency must be equal to the two CCD register frequency. It means that the user shall use either H=2 (2 taps at CLK_IN data rate) or H=10 (1 tap at 2xCLK_IN data rate). Using H=1 clock mode will provide LVAL jitter on the "slave" camera. ? Only "triggered and integration time controlled" (M=3 or M=4) can be used. These modes ensure perfect readout phase starting for each cameras. tp td Internal Clock or CLK_IN CLK_IN (case H = 10) LVAL STROBE DATA First valid pixel Last valid pixel